1. Field of the Present Invention
The present invention is in the field of integrated circuit design and, more particularly, systems and methods for verifying the correctness of a design.
2. History of Related Art
In the field of integrated circuit design, formal verification refers to the process of rigorously proving that a design satisfies its specification. Typically, the specification of a verification problem includes a netlist-based representation of the design and a set of expected values for specified nets. As an example, a verification problem may include a determination of whether a CHECKSTOP signal is ever asserted, where the CHECKSTOP signal is asserted only to indicate faults. Using formal verification, one either finds a counterexample trace depicting a sequence of values of the nets over time, similar to a simulation trace, that leads to an assertion of the CHECKSTOP signal or proves that no such trace exists.
Formal verification is often performed using state space search algorithms. Such algorithms include unbounded and bounded exhaustive searches. Bounded exhaustive searches try to find an assertion of CHECKSTOP that can occur within N time steps from an initial state of the design. Unbounded exhaustive algorithms increase N until no states are encountered that have not already been encountered for smaller values of N (a condition termed “fixed-point”). If no path from an initial state to a violating state (a state in which CHECKSTOP is asserted) is encountered before fixed-point is reached, then correctness can be inferred.
Exhaustive state space search techniques such as Boolean decision diagram (BDD) techniques and satisfiability techniques are well known. Generally, however, each step of an exhaustive state space search (whether bounded or unbounded) consumes exponential time and/or memory resources with respect to the number of registers or state holding elements in the netlist. Because of this exponential relationship, integrated circuits having a large number of registers present an enormous verification challenge. It would be desirable to implement a formal verification methodology that includes efficient design model simplification or transformation techniques to reduce the model to the greatest extent possible with given resource constraints.